The use of an access device with a storage element in memory cells is well known in the art. An ever-increasing demand for higher-density memory cell arrays has led to the development of vertical memory cell devices, such as recessed access devices (RADs). Vertical memory cell devices may enable higher-density cell arrays by offsetting an access device vertically from a storage element, which arrangement utilizes less horizontal area, termed “real estate,” on the array substrate than if the access device were offset horizontally from the storage element.
FIG. 1A is a simplified plan view of a portion of a conventional recessed access device (RAD) 100. FIG. 1B is a cross-section of the conventional recessed access device 100 along line 1B-1B (i.e., taken across each component of the recessed access device 100). FIG. 1C is a cross-section of the conventional recessed access device 100 along line 1C-1C (i.e., taken along gate 130). To assist with the orientation of the different cross-sections, x-, y-, and z-directions are shown for each figure.
The recessed access device 100 includes a first pillar 110 and a second pillar 120 coupled with a channel region 115 therebetween. The first pillar 110 may be a source region, the second pillar 120 may be a drain region, and the channel region 115 may be an active region for the recessed access device 100. The recessed access device 100 may further include a gate 130 that is separated from the first pillar 110, the second pillar 120, and the channel region 115 by a gate oxide 140. The first pillar 110, the channel region 115, and the second pillar 120 of the conventional recessed access device 100 may form PN junctions so that the recessed access device 100 device operates as a transistor. For example, the first pillar 110 may comprise an N-type material, the channel region 115 may comprise a P-type material, and the second pillar 120 may comprise an N-type material to form an NPN transistor.
As shown in FIG. 1B, the recess between the first pillar 110 and the second pillar 120 may form a U-shaped recessed region wherein the gate 130 is formed. FIG. 1B also shows that the recessed access device 100 may be formed on a substrate 105 (e.g., a P-type substrate).
As shown in FIG. 1C, the gate 130 may extend across the channel region 115 and surround the channel region 115 on at least three sides. As discussed above, both the channel region 115 and the substrate 105 comprise a P-type material. As a result, the channel region 115 and the substrate 105 may be formed from the same material. The portion of the gate 130 that extends around the channel region 115 may also be referred to as the “saddle region” because it resembles a saddle being disposed over the channel region 115. Also, the channel region 115 may be referred to as the “fin region” because it resembles a fin extending upward into the saddle region of the gate 130.
If the gate 130 has 0V applied thereto, current should not flow through the channel region 115; however, leakage may occur and current may flow through the channel region 115. Leakage may be reduced by having a relatively low doping concentration for an N-channel region 115; however, performance of the drive current may also be reduced. Performance of the drive current may be improved during operation as the doping concentration of the channel region 115 increases. Therefore, there is a tradeoff between performance during operation when the recessed access device 100 is enabled, and leakage when the recessed access device 100 is disabled depending on the doping concentration selected for the P-type material of the channel region 115.